Modeling of Schottky coupled transistor logic

The SCTL gate which promises increased speed and reduced power is discussed. It involves the use of a single lowly doped collector incorporating Schottky diodes to decode the output. A complete electrical model is formulated and compared with experimental results. The model is then used to optimize this structure with respect to extrinsic and intrinsic base doping and collector doping, and it resulted in an 8.5 ns fanout four device on a 2.5 μm epilayer. Finally, the model is used to study the possibility of Schottky clamping the base collector, and it was found that higher collector doping was needed for a minimum delay.