A gallium arsenide SDFL gate array with on-chip RAM

Author

Vu, Tho T. ; Roberts, Peter C T ; Nelson, Roderick D. ; Lee, Gary M. ; Hanzal, Brian R. ; Lee, Kang W. ; Zafar, Naeem ; Lamb, David R. ; Helix, Max J. ; Jamison, Stephen A. ; Hanka, Steven A. ; Brown, James C., Jr. ; Shur, Michael S.

Volume

19

Issue

1

fYear

1984

Firstpage

10

Lastpage

22

Abstract

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.

Keywords

Cellular arrays; cellular arrays; CMOS logic circuits; Decoding; FETs; Gallium arsenide; Logic arrays; MESFET circuits; Programmable logic arrays; Read-write memory; SRAM chips; Schottky diodes;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1984.1052078

Filename

1052078