Process and device performance of 1 μm channel n-well CMOS technology

The process and device performance of 1 μm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5×10/SUP 15/ to 4×10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 μm, channel boron implantation doses from 2×10/SUP 11/ to 1.3×10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 μm. Based on the experimental results obtained from μm-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 μm-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.