Title :
Design methodology of a 1.2-μm double-level-metal CMOS technology
Author :
Preckshot, Nancy E. ; Campbell, Stephen A. ; Heikkila, Walter W. ; Dokos, Dimitri ; Passow, Robin H. ; Grant, Wesley N. ; Schultz, Dale ; Victorey, John P.
fDate :
2/1/1984 12:00:00 AM
Abstract :
An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-μm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.
Keywords :
Digital integrated circuits; digital integrated circuits; Boron; CMOS technology; Circuits; Design methodology; Etching; Implants; Libraries; Resists; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052090
