Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Author

Kanno, Yusuke ; Mizuno, Hiroyuki ; Yasu, Yoshihiko ; Hirose, Kenji ; Shimazaki, Yasuhisa ; Hoshi, Tadashi ; Miyairi, Yujiro ; Ishii, Toshifumi ; Yamada, Tetsuya ; Irita, Takahiro ; Hattori, Toshihiro ; Yanagisawa, Kazumasa ; Irie, Naohiko

Author_Institution

Central Res. Lab., Hitachi, Ltd, Tokyo

Volume

42

Issue

1

fYear

2007

Firstpage

74

Lastpage

83

Abstract

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead

Keywords

leakage currents; low-power electronics; nanoelectronics; system-on-chip; 90 nm; clock gating; hierarchical power distribution; leakage currents; low power multiCPU SoC; power gating; power tree management rules; power tree structure; Cellular phones; Clocks; Fabrication; Large scale integration; Leakage current; MOSFETs; Power distribution; Research and development; Subthreshold current; System-on-a-chip; Common power domain; SoC; fine-grained power gating; hierarchical power distribution; leakage reduction; low power;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.885057

Filename

4039588