A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

Author

Lin, Chien-Chang ; Chen, Jia-Wei ; Chang, Hsiu-Cheng ; Yang, Yao-Chang ; Yang, Yi-Huan Ou ; Tsai, Ming-Chih ; Guo, Jiun-In ; Wang, Jinn-Shyan

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chia-Yi

Volume

42

Issue

1

fYear

2007

Firstpage

170

Lastpage

182

Abstract

In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm² silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory

Keywords

CMOS integrated circuits; SRAM chips; elemental semiconductors; high definition television; logic gates; memory architecture; silicon; video coding; 0.18 micron; 120 MHz; 320 mW; 4.5 kBytes; CMOS technology; H.264/AVC video decoder design; HD1080 video; HDTV; SRAM; Si; high definition television; low power consumption; low-cost design; real-time H.264 video decoding; Algorithm design and analysis; Automatic voltage control; CMOS technology; Decoding; Design optimization; HDTV; High definition video; Power dissipation; Random access memory; TV; H264/AVC video decoder architecture design; low power consumption; low-cost design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.886537

Filename

4039593