Parallel signature analyzers using hybrid design of their linear feedbacks

Author

Hlawiczka, Andrzej

Author_Institution

Tech. Univ. of Gliwice, Poland

Volume

41

Issue

12

fYear

1992

fDate

12/1/1992 12:00:00 AM

Firstpage

1562

Lastpage

1571

Abstract

A bottom-top exclusive OR (BTE) type multiple input linear feedback shift register (MISR) and a top-bottom exclusive OR (TBE) type MISR which use only (t+1)/2 XOR gates in their linear feedback are presented. An algebraic analysis of the operation and certain analytical results regarding the detection capability of a BTE MISR are included. Infirmities of certain BTE type MISRs and TBE type MISRs with a reducible characteristic polynomial have been made. The proof that the probability of error sequence aliasing on a single input of BTE or TBE type MISR, where a characteristic polynomial of degree n is reducible, asymptotically approaches a value greater or equal to 2^-n is also given

Keywords

logic analysers; shift registers; signal processing equipment; XOR gates; bottom-top exclusive OR; error sequence aliasing; linear feedbacks; multiple input linear feedback shift register; parallel signature analyzers; reducible characteristic polynomial; top-bottom exclusive OR; Automatic testing; Built-in self-test; Circuit testing; Feedback; Galois fields; Microprocessors; Modems; Polynomials; Shift registers; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.214664

Filename

214664