Several driving configurations with low-voltage input control for a planar power switch

Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lead to a reduction of the on-chip power dissipation and input control voltage. Moreover, the switch becomes less sensitive to tolerances in the capacitive voltage divider controlling the gate of the output transistor. An acceptable tradeoff between chip area consumed by the flip-flop arrangement, reduction of the on-chip power dissipation, and input control voltage is possible. The on-chip low-voltage control circuitry is also described.