A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

Author

Miura, Noriyuki ; Mizoguchi, Daisuke ; Inoue, Mari ; Niitsu, Kiichi ; Nakagawa, Yoshihiro ; Tago, Masamoto ; Fukaishi, Muneo ; Sakurai, Takayasu ; Kuroda, Tadahiro

Author_Institution

Dept. of Electron. & Electr. Eng., Keio Univ., Kanagawa

Volume

42

Issue

1

fYear

2007

Firstpage

111

Lastpage

122

Abstract

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10^-13

Keywords

CMOS integrated circuits; inductors; system-in-package; transceivers; 0.18 micron; 1 GHz; 1 Tbit/s; 3 W; CMOS integrated circuits; bi-phase modulation; bit-error rate; inductive-coupling transceiver; inter-chip transceiver; noise immunity; system-in-package; time division multiple access; Bit error rate; Circuit testing; Clocks; Crosstalk; Inductors; Large scale integration; Packaging; Through-silicon vias; Time division multiple access; Transceivers; Inductor; SiP; three-dimensional; wireless interconnect;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.886554

Filename

4039596