DocumentCode
895826
Title
Driving large capacitance in MOS LIS systems
Author
Nemes, Mihaly
Volume
19
Issue
1
fYear
1984
fDate
2/1/1984 12:00:00 AM
Firstpage
159
Lastpage
161
Abstract
The effect of two factors on the delay of a driver chain were analyzed. The first factor is nonzero delay of an unloaded inverter. Computer simulation shows that considerable savings in area and speed can be achieved. The second factor is the difference between propagation delay time and rinse time. Simulation showed that only a slight improvement in speed might be expected by optimizing this difference.
Keywords
Field effect integrated circuits; field effect integrated circuits; Capacitance; Delay effects; Inverters; Large scale integration; Low-frequency noise; Propagation delay; Solid state circuits; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1984.1052103
Filename
1052103
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