Title :
Driving large capacitance in MOS LIS systems
fDate :
2/1/1984 12:00:00 AM
Abstract :
The effect of two factors on the delay of a driver chain were analyzed. The first factor is nonzero delay of an unloaded inverter. Computer simulation shows that considerable savings in area and speed can be achieved. The second factor is the difference between propagation delay time and rinse time. Simulation showed that only a slight improvement in speed might be expected by optimizing this difference.
Keywords :
Field effect integrated circuits; field effect integrated circuits; Capacitance; Delay effects; Inverters; Large scale integration; Low-frequency noise; Propagation delay; Solid state circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052103
