Title :
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
Author :
Rusu, Stefan ; Tam, Simon ; Muljono, Harry ; Ayers, David ; Chang, Jonathan ; Cherkauer, Brian ; Stinson, Jason ; Benoit, John ; Varada, Raj ; Leung, Justin ; Limaye, Rahul Dilip ; Vora, Sujal
Author_Institution :
Intel Corp., Santa Clara, CA
Abstract :
This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm2 die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power
Keywords :
cache storage; integrated circuit design; logic circuits; microprocessor chips; 1 MByte; 16 MByte; 65 nm; L3 cache; circuit design; control logic; dual-core multithreaded Xeonreg processor; leakage reduction; long channel transistors; unified L2 cache; Clocks; Computer architecture; Frequency; Logic; Microprocessors; Subthreshold current; Transistors; Voltage; 65-nm process technology; Circuit design; clock distribution; computer architecture; leakage reduction; microprocessor; shared on-die cache; voltage domains;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.885041
