Delay time and signal propagation in large-scale integrated circuits

Delay time and signal propagation are considered for the logic circuits in future VLSI. When these are coupled to the necessity to dissipate power and to fundamental limits on the energy dissipation, a constraint which is almost geometry-independent is obtained. At one extreme, the fundamental limits suggest a minimum delay time of 0.01 ps. At the opposite extreme, values appropriate to conventional technology lead to a delay time per gate that is constrained to have a lower limit of about 0.2 ns in the wire-dominated chip.