Title :
Dynamic logic CMOS circuits
Author :
Friedman, V. ; Liu, S.
fDate :
4/1/1984 12:00:00 AM
Abstract :
A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.
Keywords :
Adders; adders; CMOS logic circuits; Clocks; Delay effects; Delay estimation; Frequency; Gallium arsenide; Josephson junctions; Logic arrays; Logic design; Propagation delay;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052129
