Terminal Modeling of Hardened Integrated Circuits

A technique for device terminal modeling hardened DIICs for TREE has been described. The result provides a methodology which has been successfully applied to 16 ICs described in a previous paper (Ref 1). Because of the inherent flexibility of the modeling technique presented in this paper, the authors have extended the application to include other parts including more advanced Schottky TTL devices. This also includes subroutines for beta degradation, including rapid anneal. The models can be made available through the SYSCAP II program described in Ref (3).