A bipolar 230 ps masterslice cell array with 2600 gates

A new family of high-speed bipolar masterslice cell arrays has been developed. The chips offer ECL 10K or 100K compatibility, equivalent basic gate delays of 230 ps, and integration levels up to 7600 transistors adequate for 2600 gate functions. Extensive use of three-level series-gated current-mode logic circuitry results in a minimum speed-power product of 0.37 pJ and a maximum packing density of 130 gate functions/mm/SUP 2/. The cell library contains 81 cell types, including multicell macro building blocks. A CAD system featuring both automatic cell placement and intercell routing supports the customization of the masterslices. Processing technology is characterized by 2 /spl mu/m structures, 1:1 projection lithography, ion-implanted base and emitter, oxide isolation, and three metal layers with polyimide insulation.