A defect-tolerant design for full-wafer memory LSI

Automatic defect-tolerant techniques are described for the realization of full-wafer LSI. These techniques, which are based on duplication redundancy, feature automatic inspection, detection, shift, and selection. Using these techniques, a 1.5-Mb frame static memory on a 4-in. silicon wafer (512/spl times/512 dot plane, 64 color) has been realized. The device has been fabricated using n-well CMOS technology with double-level polysilicon, double-level aluminum, and photolithography of 3-/spl mu/m dimensions. It provides typical access time of 520 ns and operating power of 5.8 W.