A VLSI memory management chip: design considerations and experience

The design of a VLSI memory measurement chip which provides the WE 32001 microprocessor with an extensive set of memory management capabilities is described. The chip is implemented in 1.75 /spl mu/m twin-tub CMOS II technology and contains 92000 transistors. Highlights of the technology are the use of twin tubs for independently optimized n- and p-channel transistors, local oxidation and self-aligned channel-stops for parasitic field protection, and the use of an n/SUP +/ substrate for latchup protection. In addition, a composite layer of TaSi over n/SUP +/ polysilicon is used to achieve a fivefold reduction in sheet resistance over the conventional n/SUP +/ polysilicon. Electrical channel lengths for n-channel and p-channel transistors are nominally 1.5 /spl mu/m.