A fast 16 bit NMOS parallel multiplier

An architecture for a fast parallel array multiplier is described. Using a 3 /spl mu/m E/D NMOS process, a 16/spl times/16 bit trial circuit has been designed. A multiplication time of 120 ns has been achieved with a power dissipation of 200 mW and a silicon area of 5 mm/SUP 2/. This architecture concept greatly reduces the logical depth of the array by rearranging internal delays. It is applicable in principle to any MOS, CMOS, GaAs, or bipolar technology.