DocumentCode :
896686
Title :
An 18 ns 4Kx4 CMOS SRAM
Author :
Childs, Larry F. ; Hirose, Ryan T.
Volume :
19
Issue :
5
fYear :
1984
Firstpage :
545
Lastpage :
551
Abstract :
A high-speed 11-mm/SUP 2/ 4K/spl times/4 CMOS static RAM fabricated developed. This circuit uses improved circuit techniques to with a single-polysilicon, single-metal process has been obtain a typical 18-ns access time with only 250 mW of active power. Among the topics discussed are the smallest single-polysilicon static RAM cell reported to date; the use of address transition assistance for equalization and boosting; a short-delay, positive-feedback boosted word line; high-speed predecoded row and column decoders; new fully compensated bit-line loads and column presence amps; and an easily implemented redundancy scheme using laser fusing techniques.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Boosting; CMOS process; CMOS technology; Cache storage; Circuits; Decoding; Delay; Laser transitions; Random access memory; Read-write memory;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1984.1052187
Filename :
1052187
Link To Document :
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