Title :
A 25 ns 64K static RAM
Author :
Yamanaka, Takashi ; Koshimaru, Shigeru ; Kudoh, Osamu ; Ozawa, Yakashi ; Yasuoka, Nobuyuki ; Ito, Hiroshi ; Asai, Hidehiro ; Harashima, Nobuyuki ; Kikuchi, Shinichi
Abstract :
A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; CMOS process; CMOS technology; Circuits; Conductors; Isolation technology; MOSFETs; National electric code; Propagation delay; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052191
