A 60 ns 256Kx1 bit DRAM using LD/SUP 3/ technology and double-level metal interconnection

A high-speed 256K/spl times/1-bit DRAM, using new circuit design techniques and a scaled n-channel process, has been developed. A row access time of 60 ns has been achieved through the use of short-channel devices and two levels of low-resistance interconnect. A staggered matrix precharge was implemented to reduce peak supply current and dI/dt during row precharge. Supply current transients are particularly important at the 256K density level due to the fast cycle rates (approaching 10 MHz) and the large matrix capacitance to be precharged.