• DocumentCode
    896795
  • Title

    A 128K wordx8 bit dynamic RAM

  • Author

    Suzuki, Shun Ichi ; Nakao, Masumi ; Takeshima, Toshio ; Yoshida, Masaaki ; Kikuchi, Masanori ; Nakamura, Kunio ; Mizukami, Takeshi ; Yanagisawa, Masayuki

  • Volume
    19
  • Issue
    5
  • fYear
    1984
  • Firstpage
    624
  • Lastpage
    627
  • Abstract
    A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.
  • Keywords
    Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Aluminum; Capacitance; Circuit noise; Coupling circuits; DRAM chips; Power dissipation; Random access memory; Testing; Wires; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1984.1052199
  • Filename
    1052199
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=896795