A 20 bit logarithmic number system processor

Author

Taylor, F.J. ; Gill, Rabinder ; Joseph, Jim ; Radke, Jeff

Author_Institution

Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA

Volume

37

Issue

2

fYear

1988

fDate

2/1/1988 12:00:00 AM

Firstpage

190

Lastpage

200

Abstract

The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performed LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared with that of the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operation and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1

Keywords

computer architecture; digital arithmetic; field effect integrated circuits; microprocessor chips; performance evaluation; satellite computers; table lookup; 20 bit; PLA; ROM; architecture; arithmetic processor; integrated Schottky logic; logarithmic number system processor; partitioned memory; performance evaluation; table lookup; Application software; Digital signal processing; Floating-point arithmetic; Hardware; Programmable logic arrays; Read only memory; Signal processing; Table lookup; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.2148

Filename

2148