Title :
A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit
Author :
Yamada, Junzo ; Mano, Tsuneo ; Inoue, Jun´ichi ; Nakajima, Shigeru ; Matsuda, Tadahito
Abstract :
A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.
Keywords :
CMOS integrated circuits; Error correction; Integrated memory circuits; Random-access storage; error correction; integrated memory circuits; random-access storage; CMOS memory circuits; Capacitors; DRAM chips; Error analysis; Error correction; Error correction codes; Random access memory; Read-write memory; Semiconductor device measurement; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052200
