Stability of nc-Si:H TFTs With Silicon Nitride Gate Dielectric

We report the fabrication and characterization of bottom-gate and top-gate nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) with amorphous-silicon nitride (a-SiN_x:H) as the gate dielectric. The devices were fabricated using standard 13.56-MHz plasma-enhanced chemical vapor deposition at 240 degC. Here, the same 80-nm nc-Si:H channel, 300-nm a-SiN_x:H gate dielectric, and 60-nm n⁺ nc-Si:H ohmic contact layers were used in both TFT structures. We analyzed the effects of gate configuration on TFT performance and, in particular, the electrical stability. The stability tests were carried out at a gate bias stress in the range from 20 to 40 V. The nc-Si:H TFTs demonstrated much better threshold-voltage (V_T ) stability compared with the amorphous-silicon (a-Si:H) counterparts, offering great promise for applications in active-matrix organic light-emitting diode (AMOLED) displays