• DocumentCode
    896858
  • Title

    Design of a FASTBUS Programmable Sequencer Module and Memory Module

  • Author

    Bertolucci, B. ; Horelick, D.

  • Author_Institution
    Stanford Linear Accelerator Center Stanford University, Stanford, California 94305
  • Volume
    29
  • Issue
    1
  • fYear
    1982
  • Firstpage
    98
  • Lastpage
    102
  • Abstract
    A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.
  • Keywords
    Circuit synthesis; Counting circuits; Fastbus; Linear accelerators; Master-slave; Protocols; Prototypes; Random access memory; Read-write memory; Registers;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1982.4335803
  • Filename
    4335803
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=896858