Probabilistic optimization for FPGA board level routing problems

Author

He, Fei ; Song, Xiaoyu ; Gu, Ming ; Yang, Guowu ; Hung, William N N ; Sun, Jiaguang

Author_Institution

Dept. of Comput. Sci., Tsinghua Univ., Beijing, China

Volume

53

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

264

Lastpage

268

Abstract

Field programmable gate arrays (FPGAs) are an enabling technology in circuit designs. We consider the board-level multi-terminal net assignment in the FPGA-based logic emulation. A novel probabilistic optimization method is devised for solving the net assignment problem. The approach incorporates randomized rounding, genetic algorithm, and solution-improvement strategies. Experimental results demonstrate promising performance.

Keywords

field programmable gate arrays; genetic algorithms; integrated circuit layout; network routing; board level routing; board-level multi-terminal net assignment; circuit design; field programmable gate arrays; genetic algorithm; logic emulation; probabilistic optimization; randomized rounding; Delay; Emulation; Field programmable gate arrays; Genetic algorithms; Hardware; Helium; Integrated circuit interconnections; Logic; Routing; Sun; Board-level routing; Chernoff bound; field programmable gate array (FPGA); randomized rounding;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2005.859569

Filename

1618893