• DocumentCode
    896871
  • Title

    Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

  • Author

    Naeemi, Azad ; Meindl, James D.

  • Author_Institution
    Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA
  • Volume
    54
  • Issue
    1
  • fYear
    2007
  • Firstpage
    26
  • Lastpage
    37
  • Abstract
    Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm2 cross-sectional area
  • Keywords
    carbon nanotubes; integrated circuit interconnections; circuit simulations; distributed circuit models; gigascale integrated systems; global interconnects; local interconnects; monolayer SWCN interconnects; multilayer SWCN interconnects; power dissipation; semiglobal interconnects; single-walled carbon nanotubes; Capacitance; Carbon nanotubes; Circuit simulation; Delay; Integrated circuit interconnections; Nonhomogeneous media; Power dissipation; Power system interconnection; Power system modeling; Voltage; Crosstalk; inductance; interconnects; molecular electronics; quantum wires; repeaters; system analysis and design; system optimization;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2006.887210
  • Filename
    4039704