A switched-capacitor implementation for video rate 2-D filters

Author

Kaufman, H.J. ; Sid-Ahmed, M.A.

Author_Institution

Dept. of Electr. Eng., Windsor Univ., Ont., Canada

Volume

39

Issue

2

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

136

Lastpage

140

Abstract

A switched-capacitor (SC) implementation for a semisystolic realization of a 2D recursive filter structure is presented. The structure is capable of operating at video rates and is amenable to VLSI fabrication, due to the application of systolic array architecture and SC circuit techniques. The folded-cascode CMOS operational amplifier (op-amp) topology is adopted because it yields high performance in high-speed SC circuits. Utilization of this type of op-amp makes it possible to minimize the settling time response that governs the upper limit of throughput rate

Keywords

CMOS integrated circuits; image processing equipment; operational amplifiers; real-time systems; switched capacitor filters; systolic arrays; video equipment; 2D recursive filter structure; SC circuit techniques; VLSI fabrication; folded-cascode CMOS operational amplifier; image processing; semisystolic realization; settling time response; switched-capacitor implementation; systolic array architecture; throughput rate; two dimensional digital filters; video rate 2-D filters; CMOS technology; Circuits; Delay effects; Digital filters; Frequency; HDTV; Hardware; Systolic arrays; TV; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.214819

Filename

214819