Author :
Palestri, P. ; Barin, N. ; Brunel, D. ; Busseret, C. ; Campera, A. ; Childs, P.A. ; Driussi, F. ; Fiegna, C. ; Fiori, G. ; Gusmeroli, R. ; Iannaccone, G. ; Karner, M. ; Kosina, H. ; Lacaita, A.L. ; Langer, E. ; Majkusiak, B. ; Compagnoni, C. Monzio ; Ponc
Abstract :
In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO2 dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance
Keywords :
Schrodinger equation; dielectric materials; leakage currents; silicon compounds; Schrodinger equation; SiO2; SiO2 dielectrics; capacitance-voltage characteristics; current-voltage characteristics; gate stacks; high-k stacks; template device structures; Capacitance; Capacitance-voltage characteristics; Circuits; Dielectric devices; Differential equations; Leakage current; Microelectronics; Schrodinger equation; Semiconductor process modeling; Tunneling; Gate leakage; gate stacks; high-$kappa$ dielectric materials; tunneling;
