A GaAs 4 kbit SRAM with direct coupled FET logic

A GaAs 4-kb static RAM with enhancement/depletion direct coupled FET logic was designed and successfully fabricated by self-aligned implantation for n/SUP +/-layer technology (SAINT). The aim of the RAM circuit was to attain an access time of 2 ns with a power dissipation of less than 1 W. Statistical circuit simulation clarified the allowable scattering tolerance for FET threshold voltage of 45 mW. In-process monitoring was made wafer-to-wafer and chip-to-chip. A minimum address access time of 2.8 ns was measured with a power consumption of 1.2 W. Write and read operations were completely confirmed with a minimum write pulse width of 2 ns.