An area-efficient approach to the design of very-large time constants in switched-capacitor integrators

A switched-capacitor integrator circuit with very high time constant using capacitive T-cells, is presented. According to a set of design equations and constraints, a test circuit previously needing an excessive capacitive ratio of over 700 has been integrated with a capacitance spread of only 25. Contrary to other designs, a simple clocking scheme is sufficient. Calculations and measurements show that in the T-cell integrator, capacitive area is conveniently traded off against amplifier specifications as open-loop and slew rate; power consumption is not necessarily compromised by these specifications. Integration of an experimental test circuit has given evidence of the ease of implementing this technique in larger systems.