Title :
A 20 ns 64K CMOS static RAM
Author :
Minato, Osamu ; Masuhara, Toshiaki ; Sasaki, Toshio ; Matsumoto, Keizo ; Sakai, Yoshio ; Hayashida, Tetsuya
Abstract :
A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3 /spl mu/m design rule are used. Good RAM performance is achieved by use of a pulsed-word-line technique and double p-well bipolar-CMOS circuitry.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Bipolar transistors; CMOS technology; Capacitance; Circuit optimization; Cutoff frequency; Flip-flops; MOSFETs; Random access memory; Read-write memory; Substrates;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1984.1052259
