An electrically reconfigurable programmable logic array using a CMOS/DMOS technology

An electrically reconfigurable programmable logic array (ERPLA) has been fabricated using a novel double diffused silicon gate (DMOS) and CMOS technology. The chip consists of all the building blocks necessary to emulate a bipolar programmable array logic (PAL). To meet the 20-pin limitation of present bipolar devices, special circuitry was used to detect read/write conditions. The test chip has a typical read access time of 70 ns and a write time of 50 /spl mu/s. Chip size is 7.6 kmils/SUP 2/.