DocumentCode :
897619
Title :
A Self-Aliglned 1-/spl mu/m-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy
Author :
Taur, Yuan ; Hu, Genda J. ; Dennard, Robert H. ; Terman, Lewis M. ; Ting, Chung-yu ; Petrillo, Karen E.
Volume :
20
Issue :
1
fYear :
1985
Firstpage :
123
Lastpage :
129
Abstract :
A six-mask 1-/spl mu/m CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p/sup +/ substrate and a retrograde n-well. Self-aligned TiSi/sub 2/ is formed on n/sup +/ and p/sup +/ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n/sup +/ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is dernonstrated that this CMOS technology is Iatchup free since the holding voltage for Iatchup is higher than 5 V.
Keywords :
CMOS integrated circuits; Integrated circuit technology; Metallisation; Titanium compounds; Boron; CMOS process; CMOS technology; Circuits; Contact resistance; Doping; Epitaxial growth; Implants; MOS devices; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1985.1052284
Filename :
1052284
Link To Document :
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