1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.