Title :
Don´t care set specifications in combinational and synchronous logic circuits
Author :
Damiani, Maurizio ; De Micheli, Giovanni
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
3/1/1993 12:00:00 AM
Abstract :
A unified framework for the specification and computation of don´t care conditions for combinational and synchronous multiple-level digital circuits is presented. Circuits are characterized in terms of graphs, logic functions and don´t care conditions induced by the external and internal interconnections. The replacement of a gate in a synchronous logic network is modeled by a perturbation of the corresponding logic function, and it is shown that the don´t care conditions for the gate optimization represent the bound on this perturbation. Algorithms to compute such don´t care conditions in both the combinational and synchronous case are presented. The implementation of the algorithms and the experimental results are discussed
Keywords :
combinatorial circuits; logic design; sequential circuits; don´t care conditions; gate optimization; graphs; logic functions; multiple-level digital circuits; synchronous logic circuits; Algorithm design and analysis; Automata; Circuit synthesis; Circuit testing; Computer networks; Digital circuits; Logic circuits; Logic functions; Minimization methods; Observability;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
