Title :
Applying simulated evolution to high level synthesis
Author :
Ly, Tai A. ; Mowchenko, Jack T.
Author_Institution :
Alberta Univ., Edmonton, Alta., Canada
fDate :
3/1/1993 12:00:00 AM
Abstract :
A general optimization algorithm known as simulated evolution (SE) is applied to the tasks of scheduling and allocation in high level synthesis. Basically, SE-based synthesis explores the design space by repeatedly ripping up parts of a design in a probabilistic manner and reconstructing them using application-specific heuristics that combine rapid design iterations and probabilistic hill climbing to achieve effective design space exploration. Benchmark results are presented to demonstrate the effectiveness of this approach. The results of a number of experiments that provide insight into why SE-based synthesis works so well are given
Keywords :
circuit layout CAD; logic CAD; optimisation; scheduling; CAD; allocation; application-specific heuristics; design space exploration; high level synthesis; optimization algorithm; probabilistic hill climbing; rapid design iterations; scheduling; simulated evolution; Circuit synthesis; Digital systems; Hardware; High level synthesis; Iterative algorithms; Lifting equipment; Scheduling algorithm; Space exploration; Strain control; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on