Power Harvester Design for Passive UHF RFID Tag Using a Voltage Boosting Technique

This paper presents a guideline to design and optimize a power harvester circuit for an RF identification transponder. A power harvester has been designed and fabricated in a CMOS 0.18- process that operates at the UHF band of 920 MHz. The circuit employs an impedance transformation circuit to boost the input RF signal that leads to the improvement of the circuit performance. The power harvester has been optimized to achieve maximum sensitivity by characterizing both the impedance transformation network and the rectifier circuit and choosing the optimum values for the circuit parameters. The measurement results show sensitivity of 14.1 dBm for dc output voltage of 1 V and the output current of 2 mum that corresponds to the output power of 2 muW.