VLSI logic and fault simulation on general-purpose parallel computers

Author

Mueller-Thuns, R.B. ; Saab, D.G. ; Damiano, R.F. ; Abraham, J.A.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

12

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

446

Lastpage

460

Abstract

The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines

Keywords

VLSI; circuit analysis computing; digital simulation; fault location; integrated logic circuits; logic CAD; parallel algorithms; VLSI; digital systems; fault simulation; general-purpose parallel computers; high-level process model; logic simulation; message-passing; parallel simulation; partitioning approach; performance model; shared-memory machines; synchronous gate-level designs; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Concurrent computing; Hardware; Logic; Message passing; Switches; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.215006

Filename

215006