Analysis of a new bit tracking loop-SCCL

The authors propose a new bit tracking loop for biphase signals which is implemented like the maximum a posteriori probability (MAP) optimal bit synchronizer by the sample-correlate choose-largest algorithm except that the estimator is sampled and moved at most one sample each bit time. A mathematical Markovian model for analysis is used. The performance of the bit tracking loop, the mean square error of the jitter and the average acquisition time, are theoretically derived. The numerical results of performance analysis for various signal-to-noise ratios are found through computer evaluations. The data obtained illustrate that this new structure is a very effective bit synchronizer for digital communications systems applying digital signal processing techniques