DocumentCode
897918
Title
An Optimized and Reliable LDD Structure for 1-/spl mu/m NMOSFET Based on Substrate Current Analysis
Author
Matsumoto, Yasuo ; Higuchi, Takayoshi ; Mizuno, Tomohisa ; Sawada, Shizuo ; Shinozaki, Satoshi ; Ozawa, Osamu
Volume
20
Issue
1
fYear
1985
Firstpage
349
Lastpage
353
Abstract
Optimization of the n/sup -/ region concentration for n-channel MOSFET´s with a lightly doped drain (LDD) structure was investigated, based on an analysis of the substrate current characteristics. When a substrate current tailing is observed, which is peculiar to the LDDFET with a low-concentration n-region, a gate current is not observed, which suggests strong resistance against hot-carrier injection. This was confirmed by a bias stress test. The optimized surface concentration for the n/sup -/ region ranges from 1 x 10/sup18/ cm/sup -3/ to 2.5 X 10/sup 18/ cm/sup -3/ under negligible V/sub TH/ shift and less than 25-percent driving capability degradation, compared to values for a conventional MOSFET.
Keywords
Insulated gate field effect transistors; Optimisation; Semiconductor device models; Acceleration; Breakdown voltage; Degradation; Etching; Fabrication; Hot carrier injection; Impact ionization; MOSFET circuits; Stress; Substrate hot electron injection;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1985.1052313
Filename
1052313
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