DocumentCode
898166
Title
Analysis and design optimization of domino CMOS logic with application to standard cells
Author
Pretorius, Jacobus A. ; Shubat, Alex S. ; Salama, C. Andre T
Volume
20
Issue
2
fYear
1985
fDate
4/1/1985 12:00:00 AM
Firstpage
523
Lastpage
530
Abstract
The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implemented in both 5- and 3-/spl mu/m CMOS processes.
Keywords
CMOS integrated circuits; Integrated logic circuits; Logic design; Optimisation; integrated logic circuits; logic design; optimisation; Analytical models; CMOS logic circuits; CMOS technology; Capacitance; Clocks; Delay; Design optimization; Logic design; Power dissipation; Semiconductor device modeling;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1985.1052338
Filename
1052338
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