Title :
Novel dynamic merged load technology
fDate :
4/1/1985 12:00:00 AM
Abstract :
Two new device concepts for dynamic ratioless inverter logic circuits are presented. Very high circuit density is achieved by replacing the traditional MOS dynamic load transistor with a novel load element which is merged with the switching transistor. Both device types can be implemented with a relatively standard double polysilicon CMOS process and are ideally suited for very low-power digital signal processors, serial memories and correlators, and digital image processors.
Keywords :
CMOS integrated circuits; Integrated logic circuits; Integrated memory circuits; Shift registers; integrated logic circuits; integrated memory circuits; shift registers; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Diodes; Inverters; Logic design; Logic devices; MOSFETs; Shift registers;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052340
