DocumentCode
898187
Title
Novel dynamic merged load technology
Author
Harari, Eli
Volume
20
Issue
2
fYear
1985
fDate
4/1/1985 12:00:00 AM
Firstpage
537
Lastpage
541
Abstract
Two new device concepts for dynamic ratioless inverter logic circuits are presented. Very high circuit density is achieved by replacing the traditional MOS dynamic load transistor with a novel load element which is merged with the switching transistor. Both device types can be implemented with a relatively standard double polysilicon CMOS process and are ideally suited for very low-power digital signal processors, serial memories and correlators, and digital image processors.
Keywords
CMOS integrated circuits; Integrated logic circuits; Integrated memory circuits; Shift registers; integrated logic circuits; integrated memory circuits; shift registers; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Diodes; Inverters; Logic design; Logic devices; MOSFETs; Shift registers;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1985.1052340
Filename
1052340
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