DocumentCode
898196
Title
Characterization of oxide trap and interface trap creation during hot-carrier stressing of n-MOS transistors using the floating-gate technique
Author
Doyle, Brian S. ; Faricelli, John ; Mistry, Kaizad R. ; Vuillaume, Dominique
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
Volume
14
Issue
2
fYear
1993
Firstpage
63
Lastpage
65
Abstract
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I/sub g/-V/sub g/ characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I/sub g/-V/sub g/ characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I/sub g/-V/sub g/ measurements.<>
Keywords
electron traps; hole traps; hot carriers; insulated gate field effect transistors; interface electron states; semiconductor device testing; I-V characteristics; changes in occupancy; floating-gate technique; gate current; gate voltage; hot-carrier stressing; interface trap creation; n-MOS transistors; oxide trapped charges; Charge pumps; Current measurement; Electron traps; Filling; Hot carriers; Interface states; Low voltage; MOSFET circuits; Stress measurement; Substrate hot electron injection;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.215109
Filename
215109
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