A high-quality stacked thermal/LPCVD gate oxide technology for ULSI

Author

Moazzami, Reza ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

14

Issue

2

fYear

1993

Firstpage

72

Lastpage

73

Abstract

By stacking thermal and high-quality LPCVD (low-pressure chemical vapor deposition) SiO/sub 2/ films, gate oxides with very low defect densities are demonstrated. Whereas previous reports suggested that a thick layer of LPCVD oxide can improve the stacked gate oxide defect density, it is demonstrated that even 25 AA of LPCVD oxide is sufficient to dramatically reduce the defect density compared to thermal oxide films. The projected scaling limit for this technology is estimated to be as low as 70 AA for the total stack thickness. An optimized thermal/LPCVD oxide technology is very promising as the gate dielectric for sub-half-micrometer CMOS technology.<>

Keywords

CMOS integrated circuits; VLSI; chemical vapour deposition; dielectric thin films; semiconductor-insulator boundaries; SiO/sub 2/ films; ULSI; high-quality films; scaling limit; stacked thermal/LPCVD gate oxide technology; sub-half-micrometer CMOS technology; very low defect densities; Annealing; CMOS technology; Dielectric films; Dielectric thin films; Electron traps; MOS devices; Semiconductor films; Silicon compounds; Stacking; Ultra large scale integration;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.215112

Filename

215112