DocumentCode :
898247
Title :
Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports
Author :
Johguchi, K. ; Zhu, Z. ; Hirakawa, T. ; Koide, T. ; Hironaka, T. ; Mattausch, H.J.
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Higashi-Hiroshima, Japan
Volume :
40
Issue :
3
fYear :
2004
Firstpage :
160
Lastpage :
162
Abstract :
A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.
Keywords :
cache storage; memory architecture; probability; data caches; distributed crossbar architecture; dynamic scheduling; instruction caches; maximum cache miss probability; multibank structure; multiport cache;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20040130
Filename :
1267514
Link To Document :
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