A 256K HCMOS ROM using a four-state cell approach

A 256K HCMOS ROM design is discussed using a geometry-variable four-state cell for high packing density. Design, area, and process margin comparisons are made to other cell approaches. The architecture of the chip is shown and device performance is summarized. The 32K/spl times/8-bit ROM has typical access times of 200 ns with 11 mA of active current at 1000-ns cycle times and typical standby currents of 300 nA. Single-layer programming is performed with the poly layer, which is in the later stages of the process cycle than field-oxide or depletion implant programmed parts. The part is produced using an n-well HCMOS process with 2-/spl mu/m poly gate lengths. The part exhibits immunity from latchup without an epi substrate layer. This is primarily due to layout procedures to insure good substrate clamping and guardbanding.