Depletion/enhancement CMOS for a lower power family of three-valued logic circuits

A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented. These circuits use two power supplies, each below the transistor´s threshold voltages, and do not include resistors. Circuit designs of basic ternary operators (inverters, NAND, NOR) are described. These basic ternary operators can be used as building blocks in the VLSI implementation of three-valued digital systems. An example of the design of a ternary full adder using this family of logic circuits is also presented.