DocumentCode :
898430
Title :
A new damascene structure for submicrometer interconnect wiring
Author :
Joshi, Rajiv V.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
14
Issue :
3
fYear :
1993
fDate :
3/1/1993 12:00:00 AM
Firstpage :
129
Lastpage :
132
Abstract :
A damascene structure for forming high-density interconnect wiring is presented. The structure results in improved open and short yields, lower sheet resistances, and comparable contact/via resistances, and it shows excellent filling of high-aspect-ratio long lines with high copper content. The key aspect of this technique is the ability to combine soft, low-resistance metal (Al alloy, Cu alloy, etc.) deposited by physical vapor deposition (PVD) with a hard metal (W) deposited by chemical vapor deposition (CVD) with high wear resistance. As a result a structure with a good polish stop, better alloying capability, and high yields can be fabricated while maintaining planarity at all levels. This structure is applied to a dense 512 K SRAM design with 0.5 mu m minimum ground rules, resulting in improved yield of partially functional chips at second-level metal compared to the conventional reactive ion etching (RIE) structure.<>
Keywords :
integrated circuit technology; metallisation; vapour deposited coatings; 0.5 micron; Al alloy; CVD; Cu alloy; HDI; SRAM design; W; chemical vapor deposition; damascene structure; hard metal; high wear resistance; high-aspect-ratio long lines; high-density interconnect; low-resistance metal; physical vapor deposition; second-level metal; submicrometer interconnect wiring; Alloying; Chemical vapor deposition; Collimators; Copper alloys; Etching; Filling; Random access memory; Tin; Ultra large scale integration; Wiring;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.215134
Filename :
215134
Link To Document :
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